The present invention relates to an information processing apparatus in which a plurality of processing units having buffer memories use a common main storage device, wherein requests by the processing units to update process information stored in the main storage device can be promptly executed without lowering the speed or accuracy of the information processing apparatus.
A method of using a buffer memory is known for reducing access time to a main storage device shared by the processing units of an information processing apparatus. According to this method, a high speed buffer memory whose capacity is smaller than that of the main storage device is arranged between the processing unit and the main storage device. A copy of information stored in the main storage device which was accessed by the processing unit is then stored in the buffer memory. When the processing unit again accesses the main storage device in this state, a check is first made to see if information to be accessed exists in the buffer memory. If it exists, the information is supplied from the buffer memory without accessing the main storage device, thereby apparently reducing the access time to the main storage device.
If in the above information processing apparatus, one of the processing units updates information for a certain memory address in the main storage device, the information corresponding to this memory address which already exists in the buffer memory of another processing unit will no longer coincide with the information found the main storage device. Thus, obviously, information located in the buffer memory which has not been updated will be inaccurate and therefore lead to false results when used for further information processing.
Therefore, in the conventional information processing apparatus, when the content of the main storage device is updated, the processing unit which is updating information sends an information updating request to the main storage device, along with a memory address at which the information to be updated is located, data, and other information. When the main storage device receives the information updating request, it updates the storage content in the designated memory address. After completion of the updating, the main storage device sends an invalidation command to invalidate the information located at the certain memory address in any buffer memory other than the buffer memory sending the request to update the information. The invalidation signal uses the same bus which was used to send the information updating request.
An example of the above discussed conventional technique is disclosed in JP-A-61-112258.
However, in such a conventional technique the same bus is used to send the information updating request to the main storage device from the processing unit, and to send the command to invalidate the non-updated information stored in the other buffer memories.
Therefore, for the time interval when the main storage device sends the invalidation command to the other processing units, access to the main storage device is foreclosed to all of the processing units. This causes the problem that each of the processing units must wait until the bus becomes free, thus causing a deterioration in the processing performance of the information processing apparatus.